Project Overview

• Project Proposal
• Report 1
• Report 2
• MOSIS Description
• Fall Presentation
• Group Members

Circuit Design

• Building Blocks
• Circular FIFO
• Multiplier
• Adder
• Matlab Filter Design

PLA Design

• Control Unit
• Coefficient ROM

System Layout

• Block Diagram
• Timing Diagram
• Floorplan
• Pin Assignment
• Design Hierarchy

Testing

• IRSIM Functional Analysis
• Crystal / SPICE Performance Analysis

Miscellaneous

• Download Web Site

This chip implements an FIR pre-processing filter for use in a digital hearing aid application. There are 4 different filters selectable by user heuristics, and each filter is 21 taps long. Both the filter input and output are in 10-bit, two’s complement format.