A 21-element, 10-bit wide circular FIFO was constructed for the FIR filter. The FIFO holds incoming data samples and cycles through them one at a time. It has 10-bit input and 10-bit output data lines, as well as load, advance, and clock signals.

The design of the FIFO is shown in Figure 1. Each block represents a single 1-bit flip-plop, while each column is a group of 21 sequential flip-flops. There are 10 "columns" in the full FIFO, albeit implemented as rows to make better use of available chip space as shown in the floorplan.

Figure 1: FIFO Design

When the load signal is low, the input to the FIFO is external to the module. In this final system, this is connected to the latched input data lines. When load is high, the FIFO output is looped around to the FIFO input, making it circular.

When the advance signal is high, the data stored in the FIFO is advanced by one stage. When the advance signal is low, the data remains in the current stage and the output is constant.

The full implementation of the FIFO is shown in Figure 2.

Click on the figure for a full-sized view

Figure 2: FIFO Implementation

Detailed implementation views of several FIFO sub-modules are also available:

• Advance Control - Controls the enable lines which manage flip-flop load/unload
• "Front" of FIFO Row - Contains input multiplexor and first flip-flop
• Flip-Flop Row - Row of 21 flip-flops, 1 deep
• Single Flip-Flop

An IRSIM simulation of the FIFO was performed to verify its functionality. The results of this simulation are shown in Figure 3.

Note that this specific simulation only shows 2 bits out of the full 10 bits the FIFO actually stores. This was done to conserve enough space to illustrate the proper operation of the FIFO with regards to its full input size (21 cycle delay) and control signals.

As shown in the above figure, 21 input samples are loaded into the FIFO, one per cycle. During this loading stage, the load line is low, indicating that the FIFO input is external to the module. The advance line is high, indicating that the FIFO storage elements should be advanced once per cycle.

After the 21st cycle, the earliest input data samples appear on the output lines. At this point, the load line (managed by the control unit), is set high, indicating that the FIFO input is the output of the FIFO. This has the effect of making the FIFO circular. Also of interest in the second half of the simulation is the drop of the advance line for several cycles, which shows how the flip-flops (which are triggered from the enable lines) hold their current value.