PLA : Control Unit

The control unit is responsible for the management of the FIR filter and its various components. The PLA initializes to the idle state, and remains there until the input enable line is asserted, notifying the control unit that new data is ready to be filtered. The control unit then loads that data into the FIFO, clears the accumulator, and triggers the ROM to begin outputting filter coefficients. In sync with the ROM output, the control unit then cycles through all 21 elements in the FIFO, and the multiply & accumulate unit automatically produces the output coefficient. Once the output coefficient is calculated, the FIFO is advanced by one extra element to clear space for the next input data. Then, the output ready line is asserted for 5 cycles, and the control unit returns to the Idle state to wait for new input data.

This process is shown in Figure 1.

Figure 1: Control Unit State Diagram

The control unit after implementation in MAGIC is shown in Figure 2.

Figure 2: Control Unit in Magic

The ROM and Control Unit PLAs were simulated together in IRSIM to better resolve any timing dependencies between the two systems. The results shown in Figure 3 clearly show the control unit starting after the input-enable line is asserted, and cycling through its state machine by holding the advance line high. It clears the accumulator and asserts the rom-cycle-start signal which triggers the ROM to also cycle through its set of stored coefficients as selected by the heuristics input. The control unit ends by asserting the output-ready signal.

Figure 3: Control Unit and ROM PLAs

Control Unit I/O Signals:

(I) RESTART - Restart PLA
(I) FAILSAFE - Enable failsafe mode (copy filter input directly to output)
(I) INPUT_ENABLE - New filter input ready
(O) INPUT_LATCH_EN - Latch filter input
(O) FIFO_LOAD - Load FIFO (0=External input, 1=Circle FIFO output back to the input)
(O) FIFO_ADVANCE - Advance FIFO by 1
(O) ADD_B_ZERO - B input to the adder is zero instead of latched adder output.
(O) ROM_CYCLE_START - Trigger ROM PLA to cycle through stored filter coefficients
(O) OUTPUT_LATCH_EN - Latch filter output
(O) OUTPUT_READY - Signal new filter output ready