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Circuit Design: Multiplier
 

A 12-bit multiplier was constructed for the FIR filter. This design uses a square version of a 12x12 array multiplier, and requires 120 full adders, 12 half adders and 144 AND gates. It has two 12-bit input lines and 24-bit product output lines, as shown in Figure 1.

Figure 1: 12-bit Multiplier Design

 

The full implementation of the multiplier is shown in Figure 2.

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Figure 2: 12-bit Multiplier Implementation

 

An IRSIM simulation of the multiplier was performed to verify its functionality. The results of this simulation are shown in Figure 3.

 

Figure 3: 12-bit Multiplier Simulation

 

A discussion of the timing results of this multiplier can be found in the Crystal/SPICE section of the report.