In this project, we are implementing an FIR pre-processing filter ASIC for use in a digital hearing
aid application. The original project timeline from the proposal is shown in Figure 1.
Figure 1: Project Timeline
When compared to the original timeline, the project is on or slightly ahead of schedule. As of
October 19th, several key tasks have been completed, while others are in-progress. Specifically,
initial project tasks, such as the algorithm design, high level block diagrams, and chip floorplanning
have been completed. In addition, cells of low-level building blocks have been constructed and
tested individually. Higher-level modules using these blocks have also been constructed and tested,
including the main adder for the FIR filter and a FIFO used to store incoming data.
To complete the module construction stage, several additional modules will need to be built, including
the multiplier (currently in-progress), ROM, and system controller. These modules should be completed
on-schedule, and thus the original project timeline should be valid for the remainder of the
project.
